1. Field of the Invention
The present invention relates to an integrated circuit (IC) automatic test system and an IC automatic test method, especially to an IC automatic test system and an IC automatic test method storing test data in scan chains. The automatic test system is formed by at least one scan chain, a test controller, and a test decompressor. Test data is provided by different connections between two adjacent scan units of each scan chain. Then the test data is reconstructed and decompressed by the test decompressor to generate the test pattern required for tests and transfer the test pattern to the scan chains of the IC for performing electrical test. Thus the IC test system and the IC test method of the present invention perform automatic tests without using external automatic test equipment (ATE) to provide test data. Therefore test cost is significantly reduced.
2. Description of Related Art
Moore's Law is the observation that the number of transistors in an integrated circuit doubles approximately every 18 months along with advancements in semiconductor manufacturing technology. That means the performance is also doubled. Nowadays the number of the components in the integrated circuit is up to tens of millions or even hundreds of millions owing to fast development of semiconductor manufacturing technology. In order to perform electrical test of such huge and complicated circuits, a large amount of test data is required to complete the test and achieve the fault coverage required.
The conventional way used to test IC is by using external automatic test equipment (ATE) that sends test control signals and test patterns to IC through test pins. The test device applies test stimuli to the IC and receives test response from the IC owing to the test control signal. The test response is obtained and compared with the expected one by the ATE to complete IC electrical test. Such test way fully relies on the ATE so that the ATE becomes a major cost source. However, huge amount of test data and the increasing components result in higher requirements of storage space and test pins. Thus the ATE is getting more expensive and the test cost of IC is a great burden to semiconductor plants or packaging and testing plants.
Refer to Taiwanese Pub. Pat. No. TW 1472778 B, an automatic retest method for system-level IC test and IC test equipment using the same are revealed. A plurality of sets of test devices is used to run IC test respectively. After completing the IC test, test results are sent to a processor for being checked whether the respective test result is over a threshold set. If not, the IC is delivered into the test device with the highest pass rate again for retesting. Thus whether the IC is over the threshold after retest can be confirmed to avoid test errors and increase the yield rate.
The ATE still plays an important role on most of IC test methods available now. In order to reduce test cost generated owing to the automatic test equipment, test data compression and built-in-test (BIST) are proposed. Although these two methods can reduce the requirements of ATE for storage space and test pins, each of them has certain limits. The test data compression still needs external ATE to transfer some necessary test patterns or signals while the BIST has the shortcomings of longer test application time and additional storage space required for storing test data.
In order to overcome shortcomings of the conventional IC test device and the IC test method mentioned above, there is room for improvement and a need to provide a novel IC test device and an IC test method.